Junction termination extensions (JTEs) and graded junction termination extensions (GJTEs) have been utilized as a device edge passivation technique in high voltage semiconductor devices such as MOSFETs, IGBTs, MCTs, bipolar transistors, thyristors, and diodes. In such devices, the maximum reverse voltage that the device can withstand is limited by the breakdown voltage of the reverse-blocking junction. However, the actual breakdown voltage of the junction normally falls short of the breakdown voltage that might ideally be achieved because of the development of excessively high field strengths at the termination of the junction between the P region and the N region, usually at a location slightly above the metallurgical junction along a region of curvature at the junction termination. The formation of JTEs that overlap and extend laterally from such junctions act to spread the high field strengths over wider areas and thereby increase the voltage at which avalanche breakdown occurs.
Various techniques, generally employing well known masking, doping, and diffusion processes, have been developed for forming JTEs and GJTEs in semiconductor devices, such as diodes, that are formed on silicon substrates. U.S. Pat. No. 4,927,772 of Arthur et al., U.S. Pat. No. 4,648,174 of Temple et al., and U.S. Pat. No. 6,215,168 of Brush et al. all disclose and discuss examples of such techniques and the disclosures of these patents are hereby incorporated by reference. Traditional masking, doping and diffusion techniques work well with semiconductor devices fabricated on silicon because dopants applied to the silicon diffuse into the silicon with relative ease at reasonable temperatures. As a result, the formation of JTEs and GJTEs in silicon-based semiconductor devices has become standard practice, particularly in higher voltage devices.
Materials other than silicon have been demonstrated to exhibit characteristics superior to silicon as a substrate in high power semiconductor devices. One such material is silicon carbide (SiC). An attractive property of SiC is that its critical field strength is over ten times that of silicon. For a given voltage rating, this high field strength translates to a two to three order of magnitude reduction in the specific on-resistance of the drill region of an SiC power device. Unfortunately, just as in silicon devices, ideal blocking voltage is difficult to achieve due to effects at the device edge. For planar devices, field line crowding causes the electric field to be higher at the perimeter than in the bulk of the device. This field crowding can cause increased leakage current and ultimately premature breakdown of the device. Field line crowding can be reduced with etched mesa isolation; however, damage from etching can also cause leakage and premature breakdown at the device edges.
Many techniques have been employed to remedy this periphery problem. Guard rings, field plates, argon implantation, and junction termination extensions (JTEs) have been used for planar SiC devices. Beveled sidewalls and multiple step etching, as well as JTEs, have been used for mesa-isolated devices. These methods have been successful for the most part, but each method has its particular drawbacks. Guard rings are often difficult to fabricate; field plates are limited by the strength of the dielectric used; argon implantation can increase reverse leakage current; beveled etching is less effective with abrupt, one-sided negative junctions, and multiple step etching complicates the beveling process with additional fabrication steps. Junction termination extensions have been widely used, but JTEs are difficult to optimize and implement with a SiC substrate and GJTEs, which require multiple zones of decreasing implant dose in order to achieve ideal breakdown for a junction, are even more difficult to implement. These difficulties are due in large measure to the fact dopants do not diffuse into the SiC substrate material as they do into silicon, except at extremely high temperatures that tend to destroy the SiC material itself. More specifically, the combination of implantation/diffusion is not feasible for SiC because almost all atoms have extremely low diffusion coefficients in SiC at temperatures below 2,000° C., which is very nearly the bulk growth temperature of SiC itself. Thus, traditional masking, implantation, and diffusion techniques typically used to create JTEs and GJTEs in silicon-based semiconductor devices simply are not available for use in SiC-based semiconductor devices.
Accordingly, a need exists for reliable techniques and methodologies for forming JTEs and GJTEs in semiconductor devices utilizing materials other than silicon, such as SiC, in order to take full advantage of the superior performance of such materials in high voltage semiconductor devices. It is to the provision of such techniques that the present invention is primarily directed.